FPGA Conference: Self organizing administration tool to control FPGA designs

Come to the FPGA Conference Europe from 4-6 July in Munich. Our software developer Dr. Harald Simmler will give a presentation on self-organising management tools for FPGA design control, on 5 July - 12:00-12:45, Track 3 - Tools & Methodologies.

Abstract of the talk:

Self organizing administration tool to control FPGA designs

Modern FPGA designs consists of numerous blocks, each with it's own register set to define the functionality. Keeping track of all modules, each with a version specific set of registers, is a complex task. A self organizing admin tool will help to conquer this task. It is able to identify the instantiated blocks on startup and dynamically load the corresponding low- and high-level library modules used to accuratly control the individual block in the design. To achieve that, a module info block is generated and connected to the bus system. Located at a fix address in the register space, it allows the administration tool to read all essential information for each module and dynamically load the drivers (low- and high level). The data in the info block consist of primary and secondary elements. Vital primary elements are module ID, and module index, a version number and the base address. Optional secondary elements are human readable names, connect information like e.g. connected devices on the I2C bus module and link information showing dependencies between modules. An automated development tool will parse the HDL code to identify the modules instantiated and automatically generate the code for the info block that is added to the FPGA design. This way each design has accurate information about instantiated modules. The administration tool only needs to have an up to date list of modules and it's drivers and can control the complete design without any configuration effort. Furthermore, no individual modifications are need to be done which lowers the maintainance time to a minimum. This new approach will speed up the entire integration task, provide early access to the design in the test phase and significantly improve stability across the life cycle of the product.

Further information: https://www.fpga-conference.eu/